1. Field of the Invention
The present invention relates generally to computers and processors, and more specifically, to scheduling instructions with different latencies.
2. Description of the Related Art
A processor retrieves and executes a sequence of instructions stored in one or more memories. Many of the instructions executed have data and/or control dependencies on earlier instructions of the sequence. Processors ordinarily schedule instructions for execution in a manner that respects the dependencies.
One such dependency concerns the availability of source and destination operands. Source and destination operands may be the respective register addresses that the instructions read and write. A source operand is available when the correct data is stored therein after earlier instructions of the instruction sequence complete their writes thereto. A destination operand is available when the instruction can write to the address after all earlier instructions of the instruction sequence have completed their reads of the address. Many processors schedule an instruction for execution in response to determining that the instruction's operands are available. Determining the availability of operands consumes time and may slow instruction processing when a large number of operands must be checked in each schedule cycle.
Modern processors may include a variety of features to increase the processing speed above that of sequential (in-order) processors. One such feature is speculative execution. In speculative execution, the processor determines expectations about dependencies before execution and checks whether the expectations turned out to be true after execution. When the expectations turn out wrong, the processor re-executes the affected instructions. Speculative execution can reduce delays caused by unresolved instruction dependencies when expectations about dependencies are accurate. A second feature, which some processors use, is superscalar processing. In superscalar processing, there are several execution units with separate entry ports. A superscalar processor can dispatch an issue group of several instructions during one clock cycle. Each instruction of the issue groups is dispatched to a different entry port. Speculative execution and superscalar processing generally need techniques for handling unresolved instruction dependencies.
Some processor pipelines stall to allow operand availability to be resolved before executing subsequent instruction. Stallable pipelines use a stall control network to handle stalls. A stall control network includes a network for sending status signals from the various pipeline stages to the stall controller and a network for broadcasting "stall" or "advance" signals from the stall controller to the various stages of the pipeline. The status signals inform the stall controller whether the results can be sent from one stage to the next for further processing. The "advance" signals enable, for example, a bank of parallel flip-flops to transmit results from one stage to the next stage. Since the receiving and broadcast networks use wires with capacitances and associated transient times, these networks cause time delays, which limit the minimum time attainable for transmitting results between the pipeline stages.
The time delays of the stall control networks are exacerbated in modern chips, which can attain substantial physical sizes and use pipelines with many stages. Both properties tend to increase the wire needed for stall control networks thereby increasing the associated time delays caused by capacitances.
Without a stall network, the processor would need to schedule one issue group during each dispatch cycle. Such timing requirements may be difficult to achieve if the processor must determine whether the registers appearing as operands of each instruction of the issue group are available in the time between dispatching subsequent issue groups. These timing requirements are even more difficult to achieve as the sizes of issue groups increase.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.